As will be familiar to those skilled in the art, Dynamic Random Access Memory (DRAM) is a type of RAM that has high-density storage, but requires regular refreshing of its contents. Conventional test systems for DRAM utilise three typical designs. For example, the test system may utilise the hardware with which the DRAM is designed to operate, running special test software. Alternatively, a processor system may be employed to test the memory at full speed and all at once. A third option is to use a lower performance processor system that tests the memory in smaller pieces.
DRAM modules requiring test may have a wide data bus and large capacity. This is particularly the case when the DRAM is designed for a large system such as a file server or workstation. Testing a large capacity, wide data bus DRAM using the first two systems set out above is therefore expensive, because of the cost of the processor technology required to access the memory. The third system, although cheaper, starts to compromise on test speed and coverage.
It is an object of the present invention to address these problems with the prior art.